Regviz

Cypress Semiconductor /psoc63 /LCD0 /DIVIDER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DIVIDER

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/LCD0/DIVIDER#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SUBFR_DIV0DEAD_DIV

Description

LCD Divider Register

Fields

SUBFR_DIV

Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long.
DEAD_DIV

Length of the dead time period in cycles. When set to zero, no dead time period exists.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data